Semiconductors are widely used in integrated circuits for electronic devices such as computers and televisions. These integrated circuits typically combine thousands or even millions of transistors on a single crystal silicon chip to perform complex functions and store data. As desired storage capacity and functionality always seem to outpace current manufacturing capabilities, a great deal of research in the semiconductor industry has traditionally focused on process improvements which allow for more transistors to be packed onto a chip of a given size. Historically, such process improvements have resulted in roughly a 13% annual decrease in the minimum feature widths achievable for transistors and interconnections.
With current miniaturization and functionality trends have come a corresponding increase in the complexity of interconnect wiring used to route signals across a chip. This wiring, which not too many years ago was limited to a single level of metal conductors, now may contain as many as five (with even more desired) stacked interconnected levels of densely packed conductors. Each level of patterned conductors is typically formed over a preferably planar insulating layer, and then gaps between neighboring conductors are filled with an insulating material such as silicon dioxide. The gap-filling task, unfortunately, becomes more difficult as wiring widths and spacings shrink, since it is generally not desirable to shrink the height (i.e. thickness) of the wiring proportionally. This condition leads to the formation of deep and narrow gaps between conductors which are difficult to fill without creating voids and discontinuities in the insulating material.
Many materials and processes are under development as next generation gap-filling solutions. One promising method is described in U.S. Pat. No. 5,089,442, issued to Olmer on Feb. 18, 1992. The '442 patent discloses a two-step silicon dioxide deposition process. During the first step, dielectric material is simultaneously deposited and sputter etched, i.e. by plasma-enhanced chemical vapor deposition (PECVD) in an externally-applied magnetic field. Sputter etching is claimed to aid gap-filling by removing dielectric material depositing on the top corners of conductors and redepositing a portion of this material in the gaps between conductors. This is said to insure that gaps fill to create a generally V-shaped dielectric surface which is smoother (edges are less sharp) than the shape of the underlying conductors. At some point, the wafer is removed to a conventional PECVD chamber (i.e. without sputter etch capability), where additional oxide is added as a second layer. Optionally, the wafer is then planarized, e.g. by polishing down to the tops of the conductors. One drawback of the '442 method is a relatively low (700 .ANG./min) net deposition rate for the sputter+deposition step. Another drawback is that the sputter+deposition step does not appear to improve, and indeed appears to impair, dielectric planarity in order to effect a "smoother" surface which does not contain imbedded voids and discontinuities.